CESOP - THE NEXT STEP IN PACKET PROCESSORS
ZARLINK'S CESOP (CIRCUIT EMULATION SERVICE OVER PACKET) TECHNOLOGY PERMITS SYNCHRONOUS DATA TRANSMISSION OVER A PACKET NETWORK WITH UP TO 64 MS DELAY, WITHOUT LOSING SYNCHRONIZATION OF THE TDM STREAMS - AN INDUSTRY FIRST!
ZARLINK has launched its ZL5011x family of packet processors onto the market, making it the first company in the industry to deliver high-capacity, high-performance TDM-to-IP/Ethernet interworking on a single chip. The key to this achievement is the first-ever integration of two critical voice/data convergence functions - network timing and synchronization, and packet processing - in a single device!
A key challenge in delivering CESoP is achieving the precise levels of network synchronization and clocking required to reliably deliver constant bit-rate voice traffic over variable bit-rate packet networks. Zarlink has met this goal by implementing more than 15 patent-pending hardware and software processing techniques that allow the ZL5011x family to deliver carrier-class voice quality in both adaptive and differential synchronization modes.
These Zarlink devices are the only packet processors capable of sending high volumes of TDM traffic - up to 32 T1/E1 streams - over IP/Ethernet networks with the same voice quality and service flexibility as conventional TDM-based telephone networks.
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With the unmatched features of the three-chip, standards-compliant ZL5011x family, designers can significantly improve the performance of TDM-to-IP/Ethernet access systems, while dramatically cutting cost, size and power consumption.
THE CHIPS
Zarlink's ZL5011x family of packet processors consists of three chips that allow equipment manufacturers to support a wide range of TDM traffic densities and data rates:
The ZL50111 provides CESoP for 32 T1/E1 ports or 1024 64-Kb/s channels, while two of the ports can also be configured to deliver high-speed T3/E3 services operating at 45 Mb/s.
The ZL50110 processes eight T1/E1 ports or 256 64-Kb/s channels, while the
ZL50114 supports four T1/E1 ports or 128 channels.
All three chips support a broad array of TDM traffic formats, including unstructured mode, structured mode and fractional N x 64 Kb/s mode.
STANDARDS COMPLIANCE
Zarlink's ZL5011x family of processors complies with the ITU-T's G.823 and G.824 specifications. The chips also comply with draft standards for native TDM circuit emulation proposed by the IETF's (Internet Engineering Task Force) PWE3 (Pseudo Wire Emulation edge-to-edge) working group.
AVAILABILITY
The ZL5011x packet processors are now in large series production. A complete reference design, an evaluation board and a software API support the devices. All three are offered in 552-pin PBGA packages.
Ivan Mitic, EXT 85
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