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MINDSPEED: HIGHSPEED LINKS AND THEIR CHALLENGES!

2009-09-01

In recent years, we have witnessed a growing requirement for higher data transmission rates in many technological areas. To meet this trend, many bus systems have migrated from parallel architectures to serial data transmission, while data transfer speeds have massively increased at the same time. PCI Express, XAUI, HDMI, DVI, fiber channel and serial digital (video) interface are just a few examples of such serial data transmission technologies.

Whereas a synchronous PCI bus (in a PC) operating at a clock rate of 33 MHz and with 32 parallel address/data lines managed a data transmission rate of 133 MBytes/s, PCI Express at a clock rate of 1.25 GHz and using only one full duplex lane essentially doubled the capacity to 250 MBytes/s – with a “lane” consisting of two lines (each made up of one differential pair), one for sending and the other for receiving. Importantly, the data transmission capacities of many of the new serial busses can be multiplied by adding additional links or lanes, with the number of required line pairs growing correspondingly. Because the specifications are continually being extended and added to, the clock and data transmission rates, too, continue to increase. For example, the latest PCIe 3.0 standard specifies data rates of 32 GigaBytes/s when using up to 32 lanes.

This combination of serialization and significantly higher data transmission rates has led to never before seen challenges for design engineers. The following are just a few examples:

  1. Differential pairs need to be arranged exactly in parallel and must also be of precisely the same length. In addition, when several lanes are used in a link, each lane must – as a general rule – be of the exact same length as the others to prevent time delays between lanes.
  2. Many high-speed applications also require flexible switching of interface connections if one desires multiple signal sources using the same protocol to be connected to a particular receiver, e.g., connecting several computers which utilize a DVI interface to a given monitor. And the same holds true for the application-dependent switching of signals from different types of senders, e.g., PCIe or XAUI, to a particular receiver.
  3. For clock and data rates of 3.2 Gbps and higher, transitions such as those occurring between the PCB and its connector or between through-hole contacts can result in discontinuities if unneeded vias are not drilled back, thus dampening signals through undesirable reflection. Should a number of such discontinuities occur in succession within a given signal path, the signal will become increasingly damped and jitter will grow continually higher at the same time. This is referred to as “closing the signal eye” as observed on the corresponding level-time diagram.


And how does one solve these problems?

Designers frequently opt to increase the number of board layers to meet the routing requirements for such complex circuit arrangements, yet this leads to significant cost increases. A more cost-effective alternative would be to use a cross-point switch (XPS), for example, which not only simplifies the complex signal routing challenges but also reduces the number of layers – and, with it, the PCB costs.

As for the problem of flexible switching connections, this can be solved by ensuring different board assembly variants are available. However, this leads to higher warehousing and administrative costs. The solution here is to use a cross-point switch that permits the selection of different configurations via a hardware pin or software control.

With respect to overcoming problem #3, it is always necessary to compensate for line losses along the signal paths in the receive direction – a process referred to as equalization. In addition, jitter needs to be removed via a reclocker and the signals must be reamplified at the output.

Figure 1 shows the eye diagram for a 2.5 Gbps signal before and after input equalization.

It may be necessary to pre-compensate for the strong natural damping that occurs as these high-speed signals pass through the system or through a cable, using a process called de- and pre-emphasis (or pre-equalization). Figure 2 compares the measured signal characteristics of a 2.5 Gbps signal with pre-emphasis switched off and on.

MINDSPEED is a leading provider of clock and data recovery solutions, as well as products for high-speed signal switching and improved signal integrity in general. The company’s product portfolio thus includes cross-point switches (XPS), clock and data recovery (CDR) products, cable equalizers, reclockers and cable drivers. The MINDSPEED XPS range extends form products with 2 inputs and 2 outputs in tiny 4mm x 4mm packages through to an XPS with 144 inputs and 144 outputs. The supported data transmission rates range from a few Mbits/s to a current high of 6.5 Gbps.

Tabelle: MINDSPEED Cross Point Switch Portfolio

The latest additions to the XPS range are the M21145 and M21165, two asynchronous 6.5 Gbps cross-point switches, with the M21145 offering 80x80 inputs/outputs and the M21165 160x160. Both solutions feature a non-blocking switching matrix and per-lane programmable input equalization, as well as output de-emphasis that can be programmed up to 6dB. The new XPS products are protocol-agnostic, to mean they are transparent and can be managed via several different interface types (2-wire I²C, 4-wire SPI, 8-bit parallel). In addition, a new configuration can be stored in a shadow register without changing the existing configuration. Switching to the new configuration can be performed via a hardware pin or software control in a matter of nanoseconds. Both the M21145 and M21165 operate with a single supply voltage of 1.2V and feature very low power dissipation per port. The devices support I/O voltages of 1.2V, 1.8V and 2.5V.

Like the new M21145 and M21165 XPS solutions, many other MINDSPEED products, too, are well suited for use with serial digital interface (SDI) applications for the professional video market. SDI is a serial digital interface technology that is primarily used for transmitting uncompressed and uncoded video data via coaxial cables. All relevant SMPTE standards and speeds are supported, to include SD- (standard definition), HD- (high definition), 2x HD- and 3G-SDI. Indeed, MINDSPEED has launched several new innovations on this front: the M21524, a dual 3G-SDI cable equalizer; the M21528, a dual 3G cable driver; and the M21350 and M21355, both quad reclockers but differing in their integrated multiplexers (the M21350 has a 4x 4:1 multiplexer, the M21355 has a 16:1 multiplexer). All four new products feature vastly reduced power consumption – up to 70% lower than existing solutions. In addition, the devices provide equally significant board space savings due to their tiny packages (4mm x 4mm 24-pin QFN for the M21524 and M21528, and a 10mm x 10mm 72-pin QFN for the M21350 and M21355).

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