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Problems with “Acoustic Noise” or “DC Bias”?

2013-11-06  Passive Components   MURATA

MURATA provides different MLCC solutions for these situations.

With certain applications, such as the consumer and lighting technology sectors, the hum caused by mechanical vibrations of ceramic capacitors can be disturbing. MURATA can provide a range of different MLCC solutions for these situations, which are available in each case in only one specific voltage and capacitance range.

Thanks to the use of a special ceramic material with a low dielectric constant, the GJ8 series allows for a certain attenuation to be achieved as shown in graphic one.

As a positive side-effect, these capacitors also offer a higher effective capacitance, because this ceramic material provides an improved DC bias characteristic.

GJ8 – Features:
Voltage range: 6.3V ~ 50V
Capacitance range: 1µF ~ 22µF
Design formats: 0603 ~ 1210
Ceramics:  X5R, X6S, X7R

MURATA is pleased to present the ZRA Series, as a new technology for the attenuation of the sound pressure level (hum) for smaller formats in particular. Because the PCB can increase the noise produced by the capacitor due to its resonance effect, an interposer board is used. This is a kind of PCB, which mechanically detaches the MLCC from the motherboard. The result is a significant reduction in acoustic noise development in comparison with standard versions. The interposer board is designed in about the same size as the particular format concerned.

ZRA – Features:
Voltage range: 4V ~ 50V
Capacitance range: 1µF ~ 47µF
Design formats: 0604 ~ 0906
Ceramics:  X5R, X6S, X7R, X7S, X7T

At present still under development is a new version of this technology (ZRB Series), in which the dimensions of the interposer board have been reduced to such an extent that the spatial area of the elements corresponds to those of conventional MLCCs. This allows for easier exchange of GRM -> ZRB, without having to adapt the PCB layout. The attenuation behavior in this situation corresponds to that of the ZRA.

The first value attained is 22µF/6.3V/0603/X5R. The intention is that this should be followed, as well as by the same types with 10V, the next smaller format, 0402, with 4.7µF (6.3V, 10V) and 10uF (6.3V) (all with X5R ceramics).

With metal terminals, MURATA provides another opportunity for reducing the transfer of vibrations onto the PCB.

This special design arrangement also allows for the mechanical stress of the connections to be absorbed.

KRM (standard):
Voltage range:  6.3V ~ 1kV
Capacitance range:  68nF ~ 47µF
Design formats:  0805 ~ 2220
Ceramics:   X5R, X6S, X7R

KCM (automotive):
Voltage range:  25V ~ 100V
Capacitance range:  4.7µF ~ 47µF
Design format: 2220
Ceramic:  X7R


KR8 (=GJ8 with metal terminal design):
25V, 10µF, 1206, X5R

A further effect of the properties of ceramic materials is the loss of capacitance when voltage is imposed, known as DC Bias.

Since the effective capacitance falls sharply as the voltage rises, the capacitor which is needed is often too large, or the capacitance value required cannot be achieved.

In a voltage range from 250V ~ 630V, Murata provides help with the GR3 type, with which a special ceramic, “X7T”, is used.

As well as the standard version GR3, a format is also available for automotive applications (GC3). The KR3 (standard) and KC3 (automotive) types are available with the metal terminal design already described.

Overview of all available types and values:
Series      Voltage           Capacitance        Design format
GR3        250 ~ 630V      10nF ~ 1µF          0805 ~ 2220

GC3        250 ~ 630V      10nF ~ 1µF          0805 ~ 2220

KR3         250 ~ 630V     100nF ~ 2.2µF            2220

KC3        250 ~ 630V      100nF ~ 2.2µF            2220


Another positive characteristic of the X7T ceramic is a reduction of the sound pressure (hum) which was referred to earlier.

For more information, feel free to contact us.

Imp_02_2013_P07_Murata_low_acoustic_noise_DC-bias_RTR4_Grafik1_Acoustic_Noise_GJ8.PNG
[Translate to English:] Grafik 1
Imp_02_2013_P07_Murata_low_acoustic_noise_DC-bias_RTR4_Grafik2_DC-Bias_GJ8_01.PNG
Grafik 2
Imp_02_2013_P07_Murata_low_acoustic_noise_DC-bias_RTR4_Grafik3_ZRA_structure.PNG
Grafik 3
Imp_02_2013_P07_Murata_low_acoustic_noise_DC-bias_RTR4_Grafik4_ZRA_graph.PNG
Grafik 4
Imp_02_2013_P07_Murata_low_acoustic_noise_DC-bias_RTR4_Grafik5_ZRB_Zeichnung_Abm.PNG
Grafik 5
Imp_02_2013_P07_Murata_low_acoustic_noise_DC-bias_RTR4_Grafik6.PNG
Grafik 6
Imp_02_2013_P07_Murata_low_acoustic_noise_DC-bias_RTR4_Grafik7_DC-Bias_GR3.PNG
Grafik 7

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