The MPM3695 Family: High-Power Module Solutions

Meeting High-Current and Precision Requirements

Powering modern applications requires high currents, precise transient control, and a flexible voltage set-up. In particular, field-programmable gate array (FPGA) power specifications often come with rigid requirements regarding output voltage (V_OUT) accuracy, where the absolute V_OUT accuracy must be around ±1.5%, regardless of temperature variations and aging. Some manufacturers’ load regulation specifications may be significantly more stringent. The most commonly used method to configure V_OUT is to use external or internal voltage dividers. This method provides flexibility for V_OUT configuration while fulfilling demanding requirements.

The MPM3695 family offers two possible methods to adjust V_OUT. The first option is to use the internal resistor voltage divider. The second option is to change V_OUT via the external resistor divider.

Figure 1 shows the typical application circuit with an internal resistor divider.

Figure 2 shows the typical application circuit with an external resistor divider.

Based on the design, it can be advantageous to utilize both methods for space-constrained applications with customization requirements. External resistor dividers can also improve thermal management, since the power dissipation can be spread across the PCB. However, one significant drawback of external resistors is that their tolerance can compromise V_OUT accuracy. Furthermore, resistor dividers have a temperature coefficient, which means their resistance can fluctuate with changes in temperature. This variation can lead to slight deviations in the feedback voltage (V_FB) and, consequently, V_OUT.

The MPM3695 family supports the PMBus protocol for the V_OUT configurations.

Table 2 shows the commands that can be used to change V_OUT.

The margin voltage commands verify the application’s robustness and ensure that the device meets the application’s specifications and can tolerate small changes in power supply voltages across time and temperature changes.

Once the selected voltage value is determined, it is compared to the V_OUT limits set by the VOUT_MAX and VOUT_MIN commands. This ensures that V_OUT remains within safe upper and lower thresholds. Finally, a scaling factor is applied to match a reference voltage.

Figure 3: The V_OUT command process for the MPM3695-10 involves using the OPERATION command to select one of the three inputs as the source of the nominal voltage (VOUT_COMMAND, VOUT_MARGIN_HIGH, or VOUT_MARGIN_LOW).

Internal Voltage Divider

V_OUT is sensed through the VOSNS+ and VOSNS- pins. The internal resistor divider reduces V_OUT to match the reference voltage (V_REF).

Figure 4 shows how to configure the internal voltage divider.

Table 3 shows the V_OUT range using the internal voltage divider option through VOUT_SCALE_LOOP (29h) and MFR_CTRL_VOUT (D1h).

While using the internal voltage divider, it is important to completely disconnect the external feedback (FB) resistors and select the appropriate voltage range according to the desired application.

A higher FB gain typically leads to faster response times to load transients. However, excessively high gains can introduce instability or overshoot. A lower FB gain can lead to slower settling times and reduced overshoot.

External Voltage Divider

When using an external voltage divider, the device’s V_OUT is scaled using two resistors (R1 and R2) connected in series to form a voltage divider configuration. V_FB is sensed through the VOSNS+ and VOSNS- pins.

Figure 5 shows an external voltage divider configuration.

The values of the FB resistors (R₂ and R₁) can be calculated with Equation 1.

Where V_REF is the reference voltage, which has a default value of 0.6V (and can be adjusted to be between 0.5V and 0.672V); and V_OUT is the target output voltage.

It is recommended to use 1% tolerance resistors with a low temperature coefficient for the FB divider. The V_OUT FB gain can be estimated with Equation 2.

For a given FB resistor network, the upper (V_{OUT_MAX}) and lower limits (V_{OUT_MIN}) of V_OUT can be calculated with Equation 3 and Equation 4, respectively.

To optimize the load transient response, a feed-forward capacitor (C_FF) must be placed in parallel with R₁ (see Figure 5).

Table 4 shows the V_OUT range when using the external voltage divider through VOUT_SCALE_LOOP (29h) and MFR_CTRL_VOUT (D1h).

Table 5 lists the values of the FB resistors and the feed-forward capacitor for common output voltages.

External Voltage Divider

The following section gives a practical example on how to set V_OUT through the external resistor voltage divider using the MPM3695-25.

Table 6 shows all parameters considered for this example.

Choose R₁ = 2kΩ and V_REF = 0.6V. Estimate R₂ with Equation 5.

Calculate the resistor divider gain with Equation 6.

V_{OUT_MAX} and V_{OUT_MIN} can be estimated with Equation 7 and Equation 8, respectively.

When using the resistor divider described above, failure to adhere to these limits reduces V_OUT accuracy.

Table 7 shows the configuration values for the nominal V_OUT command (VOUT_COMMAND) and the gain of the external resistor divider (VOUT_SCALE_LOOP) used in this example. It also includes the margin V_OUT limit commands (VOUT_MARGIN_HIGH and VOUT_MARGIN_LOW) and the safeguard V_OUT limit command (VOUT_MAX and VOUT_MIM) values.

The real output voltage (V_{OUT_REAL}) can be calculated with Equation 9.

V_{OUT_REAL} = VOUT_COMMAND if the following condition is satisfied, estimated with Equation 10.

In our current example, VOUT_SCALE_LOOP matches the resistor divider’s real gain, so V_{OUT_REAL} is equal to the value configured via VOUT_COMMAND (21h).The MPM3695-25's evaluation board (EVM3695-25-RF-02A) in a single-phase configuration was used for this example.

Figure 6 shows the circuit that was built.

MPS’s Virtual Bench Pro 4.0 GUI provides an interface to configure the MPM3695 family.

Figure 7 shows the main PMBus V_OUT commands used in this example.

The “Parameters” tab is divided into two sections. The basic parameters are found at the top, while more advanced configurations are at the bottom. Box 1 in Figure 7 shows the configurations for VOUT_COMMAND (21h), VOUT_SCALE_LOOP (29h), and MRF_CTRL_VOUT (D1h). Box 2 in Figure 7 shows the following V_OUT commands: VOUT_MAX (24h), VOUT_MIN (2Bh), VOUT_MARGIN_LOW (26h), and VOUT_MARGIN_HIGH (25h). The configuration value (in hexadecimal format) for each of these registers can be found in the “Register Map” tab in Box 3 (see Figure 7).

The MPM3695 family of power modules have telemetry commands such as READ_VIN (88h), READ_VOUT (8Bh), READ_IOUT (8Ch), and READ_TEMPERATURE (8Dh). These commands monitor the input voltage (V_IN), V_OUT, load current, and temperature in real time, respectively. The values are visualized in the “Monitoring” section in Box 4 (see Figure 7).

VOUT_COMMAND (21h) sets the nominal voltage source.

Figure 8 shows whether the values monitored in real time (indicated in the yellow box) match the target values from the application.

To set VOUT_MARGIN_HIGH (25h) as the nominal V_OUT source and turn on the device with a high margin, set OPERATION (01h), bits[5:4] = 10b. Based on Table 6, the target margin high value is set to 2V.

Figure 8 shows whether V_OUT as monitored in real time (indicated in the green box) matches the value configured via VOUT_MARGIN_HIGH (25h).

Figure 9 shows whether the result from VOUT_MARGIN_LOW (26h) matches the configured values used in this example.

Internal Voltage Divider

Consider the parameters in Table 6.

This section describes how to configure V_OUT using the internal voltage divider.

Verify that the VOSNS+ and VOSNS- pins are connected directly to the V_OUT sense points (see figure 4).

In this scenario, R₃ is set to 0Ω, and R₄ was removed in Figure 6.

For safety considerations while switching between internal and external dividers, it is highly recommended to disable the part through the EN pin; otherwise, the device could sustain damage. The V_OUT range was set via MFR_CTRL_VOUT (D1h), bits[1:0] (when set to 10b), and VOUT_SCALE_LOOP (29h) was set to 0x00FA (see Table 3).

Table 8 shows the PMBus command sequence to set V_OUT to 1.8V using the internal resistor divider.

Adjusting V_OUT on-the-fly via the PMBus interface is particularly useful when changing the I/O voltage, such as when reconfiguring the functionality of new FPGAs like the Achronix Speedster7t solution. Additionally, this on-the-fly feature can also be utilized to adjust the FPGA’s core voltage during operation to minimize power consumption.

Figure 10 shows the GUI when configuring V_OUT with the internal resistor divider, where the green box shows the commanded values for VOUT_COMMAND (21h) and MFR_CTRL_VOUT (D1h), bits[1:0]. The V_OUT current measurement, load current, and device’s temperature can be monitored in the “Monitoring” section (indicated in the yellow box) (see Figure 10).